1. Field of the Invention
The invention relates to the field of complementary metal-oxide-semiconductor (CMOS) circuits, particularly memory cells.
2. Prior Art
Complementary metal-oxide-semiconductor (CMOS) integrated circuits are well-known and widely used. Recently, this technology has become more widely used and accepted since CMOS circuits have a high immunity to "soft failures" (that is, failures associated with ionized particles traveling through the substrate). CMOS circuits have other advantages such as lower power consumption and higher noise immunity over a wide range of power supply voltages, when compared to other MOS technologies.
A CMOS process is described in copending application Ser. No. 133,580 filed Mar. 24, 1980 and entitled "CMOS Process", which application is assigned to the assignee of the present application. This process with modifications, as will be described, is used to fabricate the memory cell of the present invention. This copending application and the memory cell shown in FIG. 10 of the application represents the closest prior art known to Applicant.
As will be seen, the present invention utilizes a well-known bistable circuit (flip-flop), however, with other regions and in a unique layer to provide a memory cell which may be fabricated more densely than prior art cells and which has a higher immunity to CMOS latch-up.
The latch-up problem is a well-known problem which will be discussed in more detail in conjunction with FIG. 5. In general, CMOS circuits include transistor-like structures with adjacent NPN or PNP regions. Parasitic transistor action can occur, causing short circuits which literally destroy the CMOS circuit. A uniquely placed p-region in the present invention reduces this latch-up problem.